1. Field of the Invention
The present invention relates to a solid-state image pickup device and a method of manufacturing the same, and in particular a solid-state image pickup device in which elements of a substrate such as a well are improved in structure, to thereby improve the image quality, sensitivity and electrical characteristics of the solid-state image pickup device, and a method of manufacturing the same.
2. Description of the Related Art
In general, a so-called charge-coupled device (CCD) type of solid-state image pickup device (CCD image sensor) is well known as a solid-state image pickup device. Also, generally, the CCD image sensor is formed on an N-type substrate. The CCD image sensor needs three power supplies which are provided to have different voltage values, for driving the CCD image sensor. For example, it needs three power supplies having voltages of 5, 8 and 15 V as driving power supplies. The power consumption of such a CCD image sensor is approximately 500 mW.
Furthermore, in recent years, so-called CMOS type of amplification-type solid state image pickup devices (CMOS image sensors) have been proposed and commercialized as solid-state image pickup devices which differe in operation principle from the CCD image sensor. Such a CMOS image sensor has features different from those of the CCD image sensor. To be more specific, the CMOS image sensor has a single power supply, it can be driven with a low voltage, and the power consumption is low. For example, the CMOS image sensor has only to include a single 3V power supply. Also, the power consumption of the CMOS image sensor is approximately 50 mW.
However, recently, CMOS image sensors having a larger number of pixels (arranged at a higher density) have been manufactured. If the number of pixels is increased without changing the size of the sensor, the size of each pixel needs to be reduced. Then, the light receiving area of each photodiode also needs to be reduced. Consequently, the sensitivity of each photodiode is lowered.
On the other hand, the CMOS image sensor, as described above, is designed to be driven with a low voltage, and it is therefore difficult to widen the depletion layer of each photodiode, as compared with the CCD image sensor. Accordingly, with respect to the CMOS image sensor, it is difficult to adopt a method in which the depletion layer of the photodiode is widened to improve the sensitivity, thereby compensating for lowering of the sensitivity which is caused by further minutely forming the device. Thus, with respect to the CMOS image sensor, it is very important to develop a technique for improving the sensitivity in a method different from that in the CCD image sensor, in order that the pixels be arranged at a higher density. This is disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publications No. 2001-160620 and No. 2001-223351. In addition, it has been also required to develop a technique which lowering of the image quality such as blooming or color crosstalk can be prevented, in addition to improvement of the sensitivity.
As a measure for solving the above problem, a technique for efficiently collecting electrons in photodiodes by using, e.g., an N/P+ substrate, has been examined. The N/P+ substrate has a structure in which an N-type semiconductor layer is deposited on a P+ substrate serving as a substrate body by an epitaxial growth method. When N-type impurities such as phosphorus (P) are ion-implanted into the N-type epitaxial layer of the N/P+ substrate by an accelerator to form a photodiode (N-type semiconductor layer), the depletion layer of the photodiode can be easily widened, as compared with a P/P+ substrate. Therefore, the sensitivity of the CMOS image sensor can be improved without increasing the driving voltage of the CMOS image sensor. In addition, since the short life time of carriers can be utilized, lowering of the image quality such as blooming or color crosstalk can be prevented. Therefore, the above problem can be solved by manufacturing a CMOS image sensor by using an N/P+ substrate.
However, unlike formation of a CMOS image sensor by using a P/P+ substrate, that of a CMOS image sensor by using an N/P+ substrate has some problems specific to the N/P+ substrate. A first problem is related to isolation of a plurality of photodiodes. It should be noted that in a P/P+ substrate, a photodiodes (N-type semiconductor layers) are formed in a P-type epitaxial layer, and thus they are isolated from each other by a P-type semiconductor layer of the P-type epitaxial layer; that is, the photodiodes are not electrically connected to each other. On the other hand, in the N/P+ substrate, a plurality of photodiodes (N-type semiconductor layers) are formed in an N-type epitaxial layer, and thus they are not isolated from each other; that is, they are electrically connected to each other.
A second problem is related to leak current. In the P/P+ substrate, in a dicing step in which a single Si wafer is cut into a plurality of semiconductor chips, P-type semiconductor layers appear at cut sections of the semiconductor chips. In the N/P+ substrate, in the dicing step, PN junction surfaces, which correspond to interfaces between P-type substrate bodies and N-type epitaxial layers, appear at the cut sections of the semiconductor chips. If the PN junction surfaces appear at the sections of the chips, it is further highly possible that they may cause leakage of current at the sections, or the leak current may be increased.